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入力 | 下位桁上げ | 出力 | 上位桁上げ | |
---|---|---|---|---|
0 | 0 | 0 | 0 | 0 |
0 | 1 | 0 | 1 | 0 |
1 | 0 | 0 | 1 | 0 |
1 | 1 | 0 | 0 | 1 |
0 | 0 | 1 | 1 | 0 |
0 | 1 | 1 | 0 | 1 |
1 | 0 | 1 | 0 | 1 |
1 | 1 | 1 | 1 | 1 |
logicname sample entity add input a,b; input ci; output q; output co; switch(a,b,ci) case 0,0,0: q=0; co=0; case 0,1,0: q=1; co=0; case 1,0,0: q=1; co=0; case 1,1,0: q=0; co=1; case 0,0,1: q=1; co=0; case 0,1,1: q=0; co=1; case 1,0,1: q=0; co=1; case 1,1,1: q=1; co=1; endswitch ende endlogic |
logicname sample entity add input a,b; input ci; output q; output co; switch(a,b,ci) case 0,0,0: q=0; co=0; case 0,1,0: q=1; co=0; case 1,0,0: q=1; co=0; case 1,1,0: q=0; co=1; case 0,0,1: q=1; co=0; case 0,1,1: q=0; co=1; case 1,0,1: q=0; co=1; case 1,1,1: q=1; co=1; endswitch ende entity sim output a,b; output ci; output q; output co; bitr tc[5]; part add(a,b,ci,q,co) tc=tc+1; a=tc.0; b=tc.1; ci=tc.2; ende endlogic |