logicname sample
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity cmp
input ci,di;
input a,b;
output c,d;
if (ci & di)
c=1;
d=1;
else
if (ci)
switch(a,b)
case 0,0: c=1; d=0;
case 0,1: c=0; d=0;
case 1,0: c=0; d=1;
case 1,1: c=1; d=0;
endswitch
else
c=ci;
d=di;
endif
endif
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output ci,di;
output a,b;
output c,d;
bitr tc[4];
part cmp(ci,di,a,b,c,d)
tc=tc+1;
a=tc.0;
b=tc.1;
ci=tc.2;
di=tc.3;
ende
endlogic
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