logicname sample { -------------------------------------- } { 実効譜 } { -------------------------------------- } entity count input res; input ud; input p; output q[4]; bitr rq[4]; if (res) rq=0; else if (p) if (ud) rq = rq + 1; else rq = rq - 1; endif else rq = rq; endif endif q = rq; ende { -------------------------------------- } { 機能実行譜 } { -------------------------------------- } entity sim output res; output ud; output p; output q[4]; bitr tc[5]; part count(res,ud,p,q) tc=tc+1; if (tc==3) p=1; endif if ((tc>5)&(tc<8)) p=1; endif if ((tc>10)&(tc<16)) p=1; endif if (tc==20) res=1; endif if (tc>9) ud=0; else ud=1; endif ende endlogic |