CRC5

logicname sample

{ -------------------------------------- }
{    実効譜                              }
{ -------------------------------------- }
entity crc5
input  res;
input  sin;
output q[5];
bitr   rq[5];

   if (res)
      rq = 0;
   else
      rq.0  = rq.4 ^ sin;
      rq.2  = rq.1  ^ (rq.4 ^ sin);

      rq.1 = rq.0;
      rq.3 = rq.2;
      rq.4 = rq.3;
   endif

   q = rq;
ende

{ -------------------------------------- }
{    機能実行譜                          }
{ -------------------------------------- }
entity sim
output res;
output sin;
output q[5];
output t1p;
bitr   tc[8];
bitr   td[28];
bitr   cd[16];

   part crc5(res,sin,q)

   tc=tc+1;

   if (tc<=2) res=1; endif

   if (tc>5)
      td.1:27=td.0:26;
   else   {↓テストデータ}
      td.0:27=0b1111111111111111111111111111;
   endif

   if (tc>=10)
      cd.1:15=cd.0:14;
   else   {↓テストCRC}
      cd=0b1101000000000000;
   endif

   if (tc==10) t1p=1; endif   {←テストデータ入力終了}

   if (tc>=10)
      sin=cd.15;   {←CRC入力}
   else
      sin=td.27;   {←テストデータ入力}
   endif

ende

endlogic