logicname sample
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity dep
output q[4];
bitr rq[4];
rq = rq + 1;
q = rq;
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output q[4];
part dep(q)
ende
endlogic
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