logicname sample
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity dep
input d[4];
output q;
bitr rq;
bitr c[4];
if (d==c)
c = 0;
else
c = c + 1;
endif
if (c==0)
rq = rq + 1;
else
rq = rq;
endif
q = rq;
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output d[4];
output q;
part dep(d,q)
d=2; {<font COLOR="red">←6 分周に設定</font>}
ende
endlogic
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