2分周器

logicname sample

{ -------------------------------------- }
{    手続き譜                            }
{ -------------------------------------- }
procedure spu
input  a;
output q;
bitr   rq[2];

   switch(rq)
      case 0:
         if (a) rq = 1; endif
      case 1:
         rq = 2;
      case 2:
         if (a)
            rq = rq;
         else
            rq = 0;
         endif
   endswitch

   q = rq.0;
endp

{ -------------------------------------- }
{    実効譜                              }
{ -------------------------------------- }
entity dep
input  a;
output q;
bitr   rq;
bitn   p;

   p = spu(a);

   if (p)
      rq = rq + 1;
   else
      rq = rq;
   endif

   q = rq;
ende

{ -------------------------------------- }
{    機能実行譜                          }
{ -------------------------------------- }
entity sim
output a;
output q;
bitr   tc[4];

   part dep(a,q)

   tc=tc+1;

   a=tc.2;

ende

endlogic