可変分周器

logicname sample

{ -------------------------------------- }
{    手続き譜   上がり起点               }
{ -------------------------------------- }
procedure spu
input  a;
output q;
bitr   rq[2];

   switch(rq)
      case 0:
         if (a) rq = 1; endif
      case 1:
         rq = 2;
      case 2:
         if (a)
            rq = rq;
         else
            rq = 0;
         endif
   endswitch

   q = rq.0;
endp

{ -------------------------------------- }
{    手続き譜   下がり起点               }
{ -------------------------------------- }
procedure spd
input  a;
output q;
bitr   rq[2];

   switch(rq)
      case 0:
         if (a) rq = 1; endif
      case 1:
         if (a)
            rq = rq;
         else
            rq = 2;
         endif
      case 2: rq = 0;
   endswitch

   q = rq.1;
endp

{ -------------------------------------- }
{    実効譜                              }
{ -------------------------------------- }
entity dep
input  s[4];   {分周設定}
input  a;      {分周入力}
output q;      {分周出力}
output t0p,t1p;
output t2p[4];
bitr   rq[4];
bitn   u,d;
bitr   p;
bitn   r[4];

   r = s - 1;
   u = spu(a);
   d = spd(a);

   if (u | d)
      if (rq==r)
         rq = 0;
         p = p + 1;
      else
         rq = rq + 1;
         p = p;
      endif
   else
      rq = rq;
      p = p;
   endif

   q = p;

   t0p = u;
   t1p = d;
   t2p = rq;
ende

{ -------------------------------------- }
{    機能実行譜                          }
{ -------------------------------------- }
entity sim
output s[4];
output a;
output q;
output t0p,t1p;
output t2p[4];
bitr   tc[5];

   part dep(s,a,q,t0p,t1p,t2p)

   tc=tc+1;

   s=3;   {←3分周に設定}
   
   a=tc.2;

ende
endlogic