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logicname sample
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity mul4
input a[4],b[4];
output q[8];
bitn n0n[8],n1n[8],n2n[8],n3n[8];
if (b.0) n0n.0:3=a; endif
if (b.1) n1n.1:4=a.0:3; endif
if (b.2) n2n.2:5=a.0:3; endif
if (b.3) n3n.3:6=a.0:3; endif
q=(n0n+n1n)+(n2n+n3n);
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output a[4],b[4];
output q[8];
bitr tc[8];
part mul4(a,b,q)
tc=tc+1;
a=tc.0:3;
b=tc.4:7;
ende
endlogic
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