|
logicname sample
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity mul4
input res;
input a[4],b[4];
output q[8];
bitr ra[8],rb[4];
bitr rq[8];
if (res)
ra.0:3=a.0:3;
rb=b;
rq=0;
else
rb.0:2=rb.1:3;
ra.1:7=ra.0:6;
if (rb.0)
rq=rq+ra;
else
rq=rq;
endif
endif
q=rq;
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output res;
output a[4],b[4];
output q[8];
bitr tc[4];
bitr ta[4],tb[4];
part mul4(res,a,b,q)
if (tc.3) tc=0; else tc=tc+1; endif
if (tc.3) res=1; endif
if (tc.3)
ta=ta+1;
else
ta=ta;
endif
if ((tc.3)&(ta==15)) tb=tb+1; else tb=tb; endif
a=ta;
b=tb;
ende
endlogic
|