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logicname sample
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity parity
input res;
input a[8];
output q[4];
bitr ra[8];
bitr rq[4];
bitr c[4];
if (res)
ra=a;
rq=0;
c=0;
else
if (c<=8)
c=c+1;
else
c=c;
endif
ra.1:7=ra.0:6;
if (ra.7)
rq=rq+1;
else
rq=rq;
endif
endif
q=rq;
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output res;
output a[8];
output q[4];
bitr tc[4];
bitr ta[8];
part parity(res,a,q)
tc=tc+1;
if (tc==15) res=1; else res=0; endif
if (tc==15) ta=ta+1; else ta=ta; endif
a=ta;
ende
endlogic
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