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logicname sample
{ -------------------------------------- }
{ 手続き譜 }
{ -------------------------------------- }
procedure spu
input a;
output q;
bitr rq[2];
switch(rq)
case 0:
if (a) rq = 1; endif
case 1:
rq = 2;
case 2:
if (a)
rq = rq;
else
rq = 0;
endif
endswitch
q = rq.0;
endp
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity send
input res;
input c;
input d[8];
output q;
output eop;
bitn p;
bitr rd[10];
bitr rq;
bitr ct[4];
p = spu(c);
if (res)
q = 0;
rd.0 = 1;
rd.1:8 = d;
rd.9 = 1;
ct = 0;
else
if (p)
rd.0:8 = rd.1:9;
rq = rd.0;
if (ct==11)
ct = ct;
else
ct = ct + 1;
endif
else
rd = rd;
rq = rq;
ct = ct;
endif
endif
if (ct==11) eop = 1; endif
q = rq;
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output res;
output c;
output d[8];
output q;
bitr tc[8];
part send(res,c,d,q)
tc=tc+1;
if (tc<3) res=1; endif
if (tc<5) d=5; endif
c=tc.2;
ende
endlogic
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