8桁直列送信器 パリティ

logicname sample

{ -------------------------------------- }
{    手続き譜                            }
{ -------------------------------------- }
procedure parity
input  a[8];
output q[4];
bitn   b4s[4];
bitn   t4s[4];

   switch(a.0:3)   {下4桁の1を数えます。}
      case 0b0000: b4s=0;
      case 0b0001: b4s=1;
      case 0b0010: b4s=1;
      case 0b0011: b4s=2;
      case 0b0100: b4s=1;
      case 0b0101: b4s=2;
      case 0b0110: b4s=2;
      case 0b0111: b4s=3;
      case 0b1000: b4s=1;
      case 0b1001: b4s=2;
      case 0b1010: b4s=2;
      case 0b1011: b4s=3;
      case 0b1100: b4s=2;
      case 0b1101: b4s=3;
      case 0b1110: b4s=3;
      case 0b1111: b4s=4;
   endswitch

   switch(a.4:7)   {上4桁の1を数えます。}
      case 0b0000: t4s=0;
      case 0b0001: t4s=1;
      case 0b0010: t4s=1;
      case 0b0011: t4s=2;
      case 0b0100: t4s=1;
      case 0b0101: t4s=2;
      case 0b0110: t4s=2;
      case 0b0111: t4s=3;
      case 0b1000: t4s=1;
      case 0b1001: t4s=2;
      case 0b1010: t4s=2;
      case 0b1011: t4s=3;
      case 0b1100: t4s=2;
      case 0b1101: t4s=3;
      case 0b1110: t4s=3;
      case 0b1111: t4s=4;
   endswitch

   q=t4s+b4s;   {上と下の1の数をたして全8桁の1の数を出します。}
endp

{ -------------------------------------- }
{    手続き譜                            }
{ -------------------------------------- }
procedure spu
input  a;
output q;
bitr   rq[2];

   switch(rq)
      case 0:
         if (a) rq = 1; endif
      case 1:
         rq = 2;
      case 2:
         if (a)
            rq = rq;
         else
            rq = 0;
         endif
   endswitch

   q = rq.0;
endp

{ -------------------------------------- }
{    実効譜                              }
{ -------------------------------------- }
entity send
input  res;
input  c;
input  d[8];
output q;
output eop;
bitn   p;
bitr   rd[11];
bitr   rq;
bitr   ct[4];
bitn   pr[4];

   p = spu(c);

   pr = parity(d);

   if (res)
      q = 0;
      ct = 0;

      rd.0   = 1;
      rd.1:8 = d;
      rd.9   = pr.0;   {←奇数パリティ、偶数にしたいときは反転します。}
      rd.10  = 1;
   else
      if (p)
         rd.0:9 = rd.1:10;
         rq = rd.0;
         
         if (ct==12)
            ct = ct;
         else
            ct = ct + 1;
         endif
      else
         rd = rd;
         rq = rq;
         ct = ct;
      endif
   endif

   if (ct==12) eop = 1; endif

   q = rq;
ende

{ -------------------------------------- }
{    機能実行譜                          }
{ -------------------------------------- }
entity sim
output res;
output c;
output d[8];
output q;
bitr   tc[8];

   part send(res,c,d,q)

   tc=tc+1;

   if (tc<3)
      res=1;
   else
      if (tc==102) res=1; endif
   endif

   if (tc<5)
      d=5;
   else
      if ((tc>100)&(tc<105))
         d=11;
      endif
   endif

   c=tc.2;

ende

endlogic