下がり起点

logicname sample

{ -------------------------------------- }
{    実効譜                              }
{ -------------------------------------- }
entity sp
input  a;
output q;
bitr   rq[2];

   switch(rq)
      case 0:
         if (a) rq = 1; endif
      case 1:
         if (a)
            rq = rq;
         else
            rq = 2;
         endif
      case 2: rq = 0;
   endswitch

   q = rq.1;
ende

{ -------------------------------------- }
{    機能実行譜                          }
{ -------------------------------------- }
entity sim
output a;
output q;
bitr   tc[5];

   part sp(a,q)

   tc=tc+1;

   if ((tc>3)&(tc<8)) a=1; endif

   if (tc==13) a=1; endif

ende
endlogic