logicname sample { -------------------------------------- } { 実効譜 } { -------------------------------------- } entity sp input a; output q; bitr rq[2]; bitr t[4]; switch(rq) case 0: if (a) if (t.3) t = t; else t=t+1; endif if (t.2) rq = 1; endif endif case 1: rq = 2; case 2: if (a) rq = rq; else rq = 0; endif endswitch q = rq.0; ende { -------------------------------------- } { 機能実行譜 } { -------------------------------------- } entity sim output a; output q; bitr tc[5]; part sp(a,q) tc=tc+1; if ((tc>3)&(tc<15)) a=1; endif if (tc==20) a=1; endif ende endlogic |