logicname sample
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity sp
input a;
output q;
bitr rq[2];
if (a)
if (rq==0)
rq = 1;
else
if (rq==1)
rq = 2;
else
rq = rq;
endif
endif
endif
q = rq.0;
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output a;
output q;
bitr tc[4];
part sp(a,q)
tc=tc+1;
if ((tc>3)&(tc<8)) a=1; endif
if (tc==10) a=1; endif
ende
endlogic
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