logicname sample
{ -------------------------------------- }
{ 手続き譜 }
{ -------------------------------------- }
procedure add
input a,b;
input ci;
output pq[2];
bitn q;
bitn co;
switch(a,b,ci)
case 0,0,0: q=0; co=0;
case 0,1,0: q=1; co=0;
case 1,0,0: q=1; co=0;
case 1,1,0: q=0; co=1;
case 0,0,1: q=1; co=0;
case 0,1,1: q=0; co=1;
case 1,0,1: q=0; co=1;
case 1,1,1: q=1; co=1;
endswitch
pq.0=q;
pq.1=co;
endp
{ -------------------------------------- }
{ 実効譜 }
{ -------------------------------------- }
entity sub4
input a[4],b[4];
output q[4];
output co;
bitn n0q[2];
bitn n1q[2];
bitn n2q[2];
bitn n3q[2];
bitn nb[4];
nb=!b+1; <← b を -b にします。}
n0q=add(a.0,nb.0,0);
n1q=add(a.1,nb.1,n0q.1);
n2q=add(a.2,nb.2,n1q.1);
n3q=add(a.3,nb.3,n2q.1);
q.0=n0q.0;
q.1=n1q.0;
q.2=n2q.0;
q.3=n3q.0;
co=n3q.1;
ende
{ -------------------------------------- }
{ 機能実行譜 }
{ -------------------------------------- }
entity sim
output a[4],b[4];
output q[4];
output co;
bitr tc[8];
part sub4(a,b,q,co)
tc=tc+1;
a=tc.0:3;
b=tc.4:7;
ende
endlogic
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