書き方

論理を小さくする書き方 その1

同じ条件の if 文をいくつも書くとその数と同数の 条件論理が作られます。 例えば yahoo28a は if (a==5) の論理を3個作ります。 これを yahoo28b のように c に a==5 を代表させて if (c) のようにすると出力論理は e0a.vhd から e0b.vhd のように小さくできます。 if (a==5) は一致の論理ですが if (c) は条件付け をするだけなので小さいからです。

論理譜

logicname yahoo28a

entity main
input  a[4];
output ya,yb,yc;

   if (a==5) ya=1; endif
   if (a==5) yb=1; endif
   if (a==5) yc=1; endif

ende

endlogic
→ 
logicname yahoo28b

entity main
input  a[4];
output ya,yb,yc;

bitn   c;

   if (a==5) c=1; endif

   if (c) ya=1; endif
   if (c) yb=1; endif
   if (c) yc=1; endif

ende

endlogic

上の論理譜の出力VHDL譜は下のような差異があります。

VHDL譜

yahoo28a yahoo28b 
library IEEE;

use IEEE.std_logic_1164.all;

entity main is

   port(a2 : in    std_logic;
        a3 : in    std_logic;
        a1 : in    std_logic;
        a0 : in    std_logic;
        ya0: out   std_logic;
        yb0: out   std_logic;
        yc0: out   std_logic);

end main;

architecture RTL of main is
signal n_n20 : std_logic ;
signal n_n22 : std_logic ;
signal n_n38 : std_logic ;
signal n_n40 : std_logic ;
signal n_n56 : std_logic ;
signal n_n58 : std_logic ;

begin

n_n20 <= (a2 and not a3 and a1)
   or (a3) ;

n_n22 <= (a3 and not n_n20 and not a0)
   or (not n_n20 and not a0 and a2)
   or (not a3 and not n_n20 and not a2) ;

ya0 <= (not n_n22 and not a3 and not a2)
   or (not n_n22 and not n_n20) ;

n_n38 <= (a2 and not a3 and a1)
   or (a3) ;

n_n40 <= (a3 and not n_n38 and not a0)
   or (not n_n38 and not a0 and a2)
   or (not a3 and not n_n38 and not a2) ;

yb0 <= (not n_n40 and not a3 and not a2)
   or (not n_n40 and not n_n38) ;

n_n56 <= (a2 and not a3 and a1)
   or (a3) ;

n_n58 <= (a3 and not n_n56 and not a0)
   or (not n_n56 and not a0 and a2)
   or (not a3 and not n_n56 and not a2) ;

yc0 <= (not n_n58 and not a3 and not a2)
   or (not n_n58 and not n_n56) ;

end RTL;
→ 
library IEEE;

use IEEE.std_logic_1164.all;

entity main is

   port(a3   : in    std_logic;
        a2   : in    std_logic;
        a1   : in    std_logic;
        a0   : in    std_logic;
        ya0  : out   std_logic;
        yb0  : out   std_logic;
        yc0  : out   std_logic);

end main;

architecture RTL of main is
signal n_n18 : std_logic ;
signal n_n21 : std_logic ;
signal n_n22 : std_logic ;
signal n_n24 : std_logic ;
signal n_n25 : std_logic ;

begin

n_n18 <= (not a3 and not a2) ;

n_n21 <= (not a3 and not a2) ;

n_n22 <= (not n_n18 and not a3 and a1)
   or (not n_n18 and a3) ;

n_n24 <= (not n_n21 and not n_n22 and not a0)
   or (not n_n22 and not a3 and not a2) ;

n_n25 <= (not n_n21 and n_n22) ;

ya0 <= (not n_n24 and not n_n25) ;

yb0 <= (not n_n24 and not n_n25) ;

yc0 <= (not n_n24 and not n_n25) ;

end RTL;

論理を小さくする書き方 その2

信号 a の値によって 信号 b に設置する値を選択する 場合に比較演算子による条件付けよりも switch 文で 条件付けた方が論理が小さくできます。

論理譜

logicname sample53a

entity main
input  pc[4];
output q[4];

   if (pc==0) q=1; endif
   if (pc==1) q=2; endif
   if (pc==2) q=3; endif
   if (pc==3) q=4; endif

ende

endlogic
→ 
logicname sample53b

entity main
input  pc[4];
output q[4];

   switch(pc)
      case 0: q=1;
      case 1: q=2;
      case 2: q=3;
      case 3: q=4;
   endswitch

ende

endlogic

VHDL譜

s53a s53b 
library IEEE;

use IEEE.std_logic_1164.all;

entity main is

   port(pc2 : in    std_logic;
        pc3 : in    std_logic;
        pc1 : in    std_logic;
        pc0 : in    std_logic;
        q0  : out   std_logic;
        q1  : out   std_logic;
        q2  : out   std_logic;
        q3  : out   std_logic);

end main;

architecture RTL of main is
signal n_n19 : std_logic ;
signal n_n22 : std_logic ;
signal n_n45 : std_logic ;
signal n_n37 : std_logic ;
signal n_n40 : std_logic ;
signal n_n75 : std_logic ;
signal n_n58 : std_logic ;

begin

n_n19 <= (not pc2 and not pc3 and pc1)
   or (pc3)
   or (pc2) ;

n_n22 <= (not n_n19 and pc0)
   or (not pc3 and not pc2 and pc1)
   or (pc3)
   or (pc2) ;

q0 <= (not n_n22)
   or (n_n45) ;

q1 <= (n_n37 and not n_n40)
   or (not n_n40 and pc0)
   or (n_n45) ;

q2 <= (not n_n75 and not pc2 and not pc3) ;

q3 <= ('0') ;

n_n37 <= (not pc2 and not pc3 and pc1)
   or (pc3)
   or (pc2) ;

n_n40 <= (not pc2 and not pc3 and pc1)
   or (pc3)
   or (pc2) ;

n_n58 <= (not pc3 and not pc2 and pc0 and pc1)
   or (pc2)
   or (pc3) ;

n_n45 <= (pc2 and not n_n58)
   or (not n_n58 and pc3)
   or (not n_n58 and pc1) ;

n_n75 <= (not pc3 and not pc2 and not pc0 and pc1)
   or (not pc3 and not pc2 and not pc1) ;

end RTL;
→ 
library IEEE;

use IEEE.std_logic_1164.all;

entity main is

   port(q0 : out   std_logic;
        pc0: in    std_logic;
        pc2: in    std_logic;
        pc3: in    std_logic;
        q1 : out   std_logic;
        pc1: in    std_logic;
        q2 : out   std_logic;
        q3 : out   std_logic);

end main;

architecture RTL of main is

begin

q0 <= (not pc0 and not pc2 and not pc3) ;

q1 <= (pc0 and not pc1 and not pc2 and not pc3)
   or (not pc0 and pc1 and not pc2 and not pc3) ;

q2 <= (pc0 and pc1 and not pc2 and not pc3) ;

q3 <= ('0') ;

end RTL;

論理を小さくする書き方 その3

一致条件だけが必要な場合は switch 文を使う方が小 さな論理になります。 最も単純な例で結果を示します。

論理譜

logicname sample54a

entity main
input  a[4];
output q;

   if (a==2) q=1; endif

ende

endlogic
→ 
logicname sample54b

entity main
input  a[4];
output q;

   switch(a)
      case 2: q=1;
   endswitch

ende

endlogic

VHDL譜

library IEEE;

use IEEE.std_logic_1164.all;

entity main is

   port(a3 : in    std_logic;
        a2 : in    std_logic;
        a0 : in    std_logic;
        a1 : in    std_logic;
        q0 : out   std_logic);

end main;

architecture RTL of main is
signal n_n19 : std_logic ;

begin

n_n19 <= (not a3 and not a2 and a0 and a1)
   or (a2)
   or (a3) ;

q0 <= (a2 and not n_n19)
   or (not n_n19 and a3)
   or (not n_n19 and a1) ;

end RTL;
→ 
library IEEE;

use IEEE.std_logic_1164.all;

entity main is

   port(q0: out   std_logic;
        a0: in    std_logic;
        a1: in    std_logic;
        a2: in    std_logic;
        a3: in    std_logic);

end main;

architecture RTL of main is

begin

q0 <= (not a0 and a1 and not a2 and not a3) ;

end RTL;