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{    74LP02                                             }
{ ===================================================== }
logicname 74LP02

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{    実効譜                                             }
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entity TTL
input  A1,A2;
input  B1,B2;
input  C1,C2;
input  D1,D2;
output Y1,Y2,Y3,Y4;

   Y1 = !(A1 | A2) ;
   Y2 = !(B1 | B2) ;
   Y3 = !(C1 | C2) ;
   Y4 = !(D1 | D2) ;

ende

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{    機能実行譜                                         }
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entity sim
output A1,A2;
output B1,B2;
output C1,C2;
output D1,D2;
output Y1,Y2,Y3,Y4;
bitr   tc[5];

   part TTL(A1,A2,B1,B2,C1,C2,D1,D2,Y1,Y2,Y3,Y4)

   tc=tc+1;

   switch(tc)
      case 3:  A1=0; A2=0;
      case 4:  A1=0; A2=1;
      case 5:  A1=1; A2=0;
      case 6:  A1=1; A2=1;

      case 7:  B1=0; B2=0;
      case 8:  B1=0; B2=1;
      case 9:  B1=1; B2=0;
      case 10: B1=1; B2=1;

      case 11: C1=0; C2=0;
      case 12: C1=0; C2=1;
      case 13: C1=1; C2=0;
      case 14: C1=1; C2=1;

      case 15: D1=0; D2=0;
      case 16: D1=0; D2=1;
      case 17: D1=1; D2=0;
      case 18: D1=1; D2=1;
   endswitch

ende
endlogic