{ ===================================================== }
{    74LP04                                             }
{ ===================================================== }
logicname 74LP04

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{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  A,B,C,D,E,F;
output Y1,Y2,Y3,Y4,Y5,Y6;

   Y1 = !A ;
   Y2 = !B ;
   Y3 = !C ;
   Y4 = !D ;
   Y5 = !E ;
   Y6 = !F ;

ende

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{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output A,B,C,D,E,F;
output Y1,Y2,Y3,Y4,Y5,Y6;
bitr   tc[5];

   part TTL(A,B,C,D,E,F,Y1,Y2,Y3,Y4,Y5,Y6)

   tc=tc+1;

   switch(tc)
      case 3:  A=1;
      case 4:  B=1;
      case 5:  C=1;
      case 6:  D=1;
      case 7:  E=1;
      case 8:  F=1;
  endswitch

ende
endlogic