{ ===================================================== }
{    74LP10                                             }
{ ===================================================== }
logicname 74LP10

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{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  A[3];
input  B[3];
input  C[3];
output Y1,Y2,Y3;

   Y1 = !(A.0 & A.1 & A.2) ;
   Y2 = !(B.0 & B.1 & B.2) ;
   Y3 = !(C.0 & C.1 & C.2) ;

ende

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{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output A[3];
output B[3];
output C[3];
output Y1,Y2,Y3;
bitr   tc[5];

   part TTL(A,B,C,Y1,Y2,Y3)

   tc=tc+1;

   switch(tc)
      case 3:  A=0;
      case 4:  A=1;
      case 5:  A=2;
      case 6:  A=3;
      case 7:  A=4;
      case 8:  A=5;
      case 9:  A=6;
      case 10: A=7;

      case 11: B=0;
      case 12: B=1;
      case 13: B=2;
      case 14: B=3;
      case 15: B=4;
      case 16: B=5;
      case 17: B=6;
      case 18: B=7;

      case 19: C=0;
      case 20: C=1;
      case 21: C=2;
      case 22: C=3;
      case 23: C=4;
      case 24: C=5;
      case 25: C=6;
      case 26: C=7;
   endswitch

ende

endlogic