{ ===================================================== }
{    74LP109                                            }
{ ===================================================== }
logicname 74LP109

{ ----------------------------------------------------- }
{    手続き譜                                           }
{ ----------------------------------------------------- }
procedure jk
input  CP;
input  PRE;
input  CLR;
input  J,K;
output Q[2];
bitr   q;
bitr   p[2];

   if (CP)
      p=0;
   else
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            if (p==2) p=p; endif
         endif
      endif
   endif

   if (CLR)
      if (PRE)
         if (p.0)
            switch(J,K)
               case 0,1: q=q;
               case 0,0: q=0;
               case 1,1: q=1;
               case 1,0: q=!q;
            endswitch
         else
            q=q;
         endif
      else
         q=1;
      endif
   endif

   Q.0=q;
   Q.1=p.0;

endp

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CPA,CPB;
input  PRA,PRB;
input  CLRA,CLRB;
input  JA,JB;
input  KA,KB;
output PQA,NQA,PA;
output PQB,NQB,PB;
bitn   qa[2];
bitn   qb[2];

   qa=jk(CPA,PRA,CLRA,JA,KA);
   qb=jk(CPB,PRB,CLRB,JB,KB);

   PQA=qa.0;
   NQA=!qa.0;
   PA=qa.1;

   PQB=qb.0;
   NQB=!qb.0;
   PB=qb.1;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CPA,CPB;
output PRA,PRB;
output CLRA,CLRB;
output JA,JB;
output KA,KB;
output PQA,NQA,PA;
output PQB,NQB,PB;
bitr   tc[7];

   part TTL(CPA,CPB,PRA,PRB,CLRA,CLRB,JA,JB,KA,KB
           ,PQA,NQA,PA,PQB,NQB,PB)

   tc=tc+1;

   CPA=tc.2;
   CPB=tc.2;

{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
{    A                                                  }
{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
   if ((tc>39)&(tc<42)) PRA=0; else PRA=1; endif

   if (tc>4)
      if ((tc>47)&(tc<50))
         CLRA=0;
      else
         CLRA=1;
      endif
   endif

   switch(tc)
      case 8:  JA=1; KA=1;
      case 9:  JA=1; KA=1;
      case 10: JA=1; KA=1;

      case 16: JA=0; KA=0;
      case 17: JA=0; KA=0;
      case 18: JA=0; KA=0;

      case 24: JA=1; KA=0;
      case 25: JA=1; KA=0;
      case 26: JA=1; KA=0;

      case 32: JA=1; KA=0;
      case 33: JA=1; KA=0;
      case 34: JA=1; KA=0;
  endswitch

{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
{    B                                                  }
{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
   if ((tc>39)&(tc<42)) PRB=0; else PRB=1; endif

   if (tc>4)
      if ((tc>47)&(tc<50))
         CLRB=0;
      else
         CLRB=1;
      endif
   endif

   switch(tc)
      case 8:  JB=1; KB=1;
      case 9:  JB=1; KB=1;
      case 10: JB=1; KB=1;

      case 16: JB=0; KB=0;
      case 17: JB=0; KB=0;
      case 18: JB=0; KB=0;

      case 24: JB=1; KB=0;
      case 25: JB=1; KB=0;
      case 26: JB=1; KB=0;

      case 32: JB=1; KB=0;
      case 33: JB=1; KB=0;
      case 34: JB=1; KB=0;
  endswitch

ende

endlogic