{ ===================================================== }
{    74LP131                                            }
{ ===================================================== }
logicname 74LP131

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CP;
input  G1,G2;
input  D[3];
output Y[8];
output P;
bitr   d[3];
bitr   p[2];

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   endif

   if (p.0)
      d=D;
   else
      d=d;
   endif

   if (G1&!G2)
      switch(d)
         case 0: Y=0b11111110;
         case 1: Y=0b11111101;
         case 2: Y=0b11111011;
         case 3: Y=0b11110111;
         case 4: Y=0b11101111;
         case 5: Y=0b11011111;
         case 6: Y=0b10111111;
         case 7: Y=0b01111111;
      endswitch
   else
      Y=0b11111111;
   endif

   P=p.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CP;
output G1,G2;
output D[3];
output Y[8];
output P;
bitr   tc[8];
   
   part TTL(CP,G1,G2,D,Y,P)

   tc=tc+1;

   CP=tc.2;

   G1=1;

   if ((tc>3)&(tc<7))   D=0; endif
   if ((tc>11)&(tc<15)) D=1; endif
   if ((tc>19)&(tc<23)) D=2; endif
   if ((tc>27)&(tc<31)) D=3; endif
   if ((tc>35)&(tc<39)) D=4; endif
   if ((tc>43)&(tc<47)) D=5; endif
   if ((tc>51)&(tc<55)) D=6; endif
   if ((tc>59)&(tc<63)) D=7; endif
   if (tc>67) G2=1; endif

ende

endlogic