{ ===================================================== }
{    74LP138                                            }
{ ===================================================== }
logicname 74LP138

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  G1,G2A,G2B;
input  D[3];
output Y[8];
bitn   y[8];

   if (G1&!G2A&!G2B)
      switch(D)
         case 0: y=0b00000001;
         case 1: y=0b00000010;
         case 2: y=0b00000100;
         case 3: y=0b00001000;
         case 4: y=0b00010000;
         case 5: y=0b00100000;
         case 6: y=0b01000000;
         case 7: y=0b10000000;
      endswitch
   else
      y=0;
   endif

   Y=!y;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output G1,G2A,G2B;
output D[3];
output Y[8];
bitr   tc[8];

   part TTL(G1,G2A,G2B,D,Y)

   tc=tc+1;

   if (tc<8)
      G1=1; G2A=0; G2B=0;
      D=tc.0:2;
   else
      switch(tc)
         case 9:  G1=0; G2A=0; G2B=0;
         case 10: G1=0; G2A=0; G2B=1;
         case 11: G1=0; G2A=1; G2B=0;
         case 12: G1=0; G2A=1; G2B=1;
         case 13: G1=1; G2A=0; G2B=0;
         case 14: G1=1; G2A=0; G2B=1;
         case 15: G1=1; G2A=1; G2B=0;
         case 16: G1=1; G2A=1; G2B=1;
      endswitch
   endif

ende

endlogic