{ ===================================================== }
{    74LP147                                            }
{ ===================================================== }
logicname 74LP147

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  D[9];
output Y[4];
bitn   y[4];

   if (D==0x1FF)
      y=0;
   else
      if (!D.8)
         y=9;
      else
         if (D.7:8==0b10)
            y=8;
         else
            if (D.6:8==0b110)
               y=7;
            else
               if (D.5:8==0b1110)
                  y=6;
               else
                  if (D.4:8==0b11110)
                     y=5;
                  else
                     if (D.3:8==0b111110)
                        y=4;
                     else
                        if (D.2:8==0b1111110)
                           y=3;
                        else
                           if (D.1:8==0b11111110)
                              y=2;
                           else
                              if (D.0:8==0b111111110)
                                 y=1;
                              endif
                           endif
                        endif
                     endif
                  endif
               endif
            endif
         endif
      endif
   endif

   Y=!y;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
input  D[9];
output Y[4];
bitr   tc[4];

   part TTL(D,Y)

   tc=tc+1;

   switch(tc)
      case 5:  D=0b111111111;
      case 6:  D=0b000000000;
      case 7:  D=0b111111110;
      case 8:  D=0b111111100;
      case 9:  D=0b111111000;
      case 10: D=0b111110000;
      case 11: D=0b111100000;
      case 12: D=0b111000000;
      case 13: D=0b110000000;
      case 14: D=0b100000000;
   endswitch

ende

endlogic