{ ===================================================== }
{    74LP148                                            }
{ ===================================================== }
logicname 74LP148

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  EI;
input  D[8];
output Y[3];
output GS,EO;

   if (EI)
      Y=0b111;
      GS=1; EO=1;
   else
      if (D==0xFF)
         Y=0b111;
         GS=1; EO=0;
      else
         if (!D.7)
            Y=0;
            GS=0; EO=1;
         else
            if (D.6:7==0b10)
               Y=1;
               GS=0; EO=1;
            else
               if (D.5:7==0b110)
                  Y=2;
                  GS=0; EO=1;
               else
                  if (D.4:7==0b1110)
                     Y=3;
                     GS=0; EO=1;
                  else
                     if (D.3:7==0b11110)
                        Y=4;
                        GS=0; EO=1;
                     else
                        if (D.2:7==0b111110)
                           Y=5;
                           GS=0; EO=1;
                        else
                           if (D.1:7==0b1111110)
                              Y=6;
                              GS=0; EO=1;
                           else
                              if (D.0:7==0b11111110)
                                 Y=7;
                                 GS=0; EO=1;
                              endif
                           endif
                        endif
                     endif
                  endif
               endif
            endif
         endif
      endif
   endif

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output EI;
output D[8];
output Y[3];
output GS,EO;
bitr   tc[4];

   part TTL(EI,D,Y,GS,EO)

   tc=tc+1;

   switch(tc)
      case 5:  D=0b11111111;
      case 6:  D=0b00000000;
      case 7:  D=0b11111110;
      case 8:  D=0b11111100;
      case 9:  D=0b11111000;
      case 10: D=0b11110000;
      case 11: D=0b11100000;
      case 12: D=0b11000000;
      case 13: D=0b10000000;
   endswitch

   if ((tc>=5)&(tc<=14)) EI=0; else EI=1; endif

ende

endlogic