{ ===================================================== }
{    74LP151                                            }
{ ===================================================== }
logicname 74LP151

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  ST;
input  D[8];
input  SEL[3];
output PQ,NQ;
bitn   q;

   if (ST)
      q=0;
   else
      switch(SEL)
         case 0: q=D.0;
         case 1: q=D.1;
         case 2: q=D.2;
         case 3: q=D.3;
         case 4: q=D.4;
         case 5: q=D.5;
         case 6: q=D.6;
         case 7: q=D.7;
      endswitch
   endif

   PQ=q;
   NQ=!q;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output ST;
output D[8];
output SEL[3];
output PQ,NQ;
bitr   tc[5];

   part TTL(ST,D,SEL,PQ,NQ)
   
   tc=tc+1;

   switch(tc)
      case 5:  D.0=0; SEL=0;
      case 6:  D.0=1; SEL=0;
      case 7:  D.1=0; SEL=1;
      case 8:  D.1=1; SEL=1;
      case 9:  D.2=0; SEL=2;
      case 10: D.2=1; SEL=2;
      case 11: D.3=0; SEL=3;
      case 12: D.3=1; SEL=3;
      case 13: D.4=0; SEL=4;
      case 14: D.4=1; SEL=4;
      case 15: D.5=0; SEL=5;
      case 16: D.5=1; SEL=5;
      case 17: D.6=0; SEL=6;
      case 18: D.6=1; SEL=6;
      case 19: D.7=0; SEL=7;
      case 20: D.7=1; SEL=7;
   endswitch

   if ((tc>=5)&(tc<=22)) ST=0; else ST=1; endif

ende

endlogic