{ ===================================================== }
{    74LP154                                            }
{ ===================================================== }
logicname 74LP154

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  G1,G2;
input  D[4];
output Y[16];
bitn   y[16];

   if (!G1&!G2)
      switch(D)
         case 0:  y=0b0000000000000001;
         case 1:  y=0b0000000000000010;
         case 2:  y=0b0000000000000100;
         case 3:  y=0b0000000000001000;
         case 4:  y=0b0000000000010000;
         case 5:  y=0b0000000000100000;
         case 6:  y=0b0000000001000000;
         case 7:  y=0b0000000010000000;
         case 8:  y=0b0000000100000000;
         case 9:  y=0b0000001000000000;
         case 10: y=0b0000010000000000;
         case 11: y=0b0000100000000000;
         case 12: y=0b0001000000000000;
         case 13: y=0b0010000000000000;
         case 14: y=0b0100000000000000;
         case 15: y=0b1000000000000000;
      endswitch
   else
      y=0;
   endif

   Y=!y;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output G1,G2;
output D[4];
output Y[16];
bitr   tc[5];

   part TTL(G1,G2,D,Y)
   
   tc=tc+1;

   if (tc>15)
      D=0;
   else
      D=tc.0:3;
   endif

   if (tc>17)
      G1=tc.0;
      G2=tc.1;
   else
      G1=0; G2=0;
   endif

ende

endlogic