{ ===================================================== }
{    74LP164                                            }
{ ===================================================== }
logicname 74LP164

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  CP;
input  A,B;
output Q[8];
output TP;
bitr   q[8];
bitr   p[2];

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (CLR)
      if (p.0)
         q.0=A & B;
         q.1:7=q.0:6;
      else
         q=q;
      endif
   else
      q=0;
   endif

   Q=q;
   TP=p.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output CP;
output A,B;
output Q[8];
output TP;
bitr   tc[8];

   part TTL(CLR,CP,A,B,Q,TP)

   tc=tc+1;

   if ((tc>3)&(tc<70)) CLR=1; else CLR=0; endif

   switch(tc)
      case 10: A=1; B=1;
      case 11: A=1; B=1;
      case 50: A=1; B=1;
      case 51: A=1; B=1;
   endswitch


   if (tc>55) CP=0; else CP=tc.1; endif

ende

endlogic