{ ===================================================== }
{    74LP165                                            }
{ ===================================================== }
logicname 74LP165

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CIH;
input  CP;
input  SL;
input  SI;
input  D[8];
output PQ,NQ;
output TP_p;
output TP_q[8];
bitr   q[8];
bitr   p[2];

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (SL)
      if (p.0)
         if (CIH)
            q=q;
         else
            q.0=SI;
            q.1:7=q.0:6;
         endif
      else
         q=q;
      endif
   else
      q=D;
   endif

   PQ=q.7;
   NQ=!q.7;

   TP_p=p.0;
   TP_q=q;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CIH;
output CP;
output SL;
output SI;
output D[8];
output PQ,NQ;
output TP_p;
output TP_q[8];
bitr   tc[8];

   part TTL(CIH,CP,SL,SI,D,PQ,NQ,TP_p,TP_q)

   tc=tc+1;

   if ((tc>3)&(tc<50)) SL=1; else SL=0; endif

   switch(tc)
      case 10: SI=1;
      case 11: SI=1;
   endswitch

   if (tc>55) CP=0; else CP=tc.1; endif
   D=0x55;

ende

endlogic