{ ===================================================== }
{    74LP173                                            }
{ ===================================================== }
logicname 74LP173

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  CP;
input  G1,G2;
input  M,N;
input  D[4];
inout  Q[4];
output TP_Q[4];
output TP_p;
bitr   q[4];
bitn   nc[4];
bitr   p[2];
bitn   cnt;

   enable(Q,nc,q,cnt)

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (CLR)
      q=0;
   else
      if (p.0)
         if (!G1 & !G2)
            q=D;
         else
            q=q;
         endif
      else
         q=q;
      endif
   endif

   cnt=!M & !N;

   TP_Q=q;
   TP_p=p.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output CP;
output G1,G2;
output M,N;
output D[4];
output Q[4];
output TP_Q[4];
output TP_p;
bitr   tc[8];

   part TTL(CLR,CP,G1,G2,M,N,D,Q,TP_Q,TP_p)

   tc=tc+1;

   if ((tc>3)&(tc<18)) CLR=0; else CLR=1; endif
   CP=tc.1;

   if (tc>9) D=10; else D=5; endif

   switch(tc)
      case 10: G1=1; G2=1;
      case 11: G1=1; G2=1;
      case 12: G1=1; G2=1;
      case 13: G1=1; G2=1;
   endswitch

   M=0; N=0;

ende

endlogic