{ ===================================================== }
{    74LP192                                            }
{ ===================================================== }
logicname 74LP192

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  CPU,CPD;
input  LD;
input  D[4];
output Q[4];
output CR,BR;
output TP_pu,TP_pd;
bitr   q[4];
bitr   pu[2];
bitr   pd[2];

   if (CPU)
      if (pu==0)
         pu=1;
      else
         if (pu==1)
            pu=2;
         else
            pu=pu;
         endif
      endif
   else
      pu=0;
   endif

   if (CPD)
      if (pd==0)
         pd=1;
      else
         if (pd==1)
            pd=2;
         else
            pd=pd;
         endif
      endif
   else
      pd=0;
   endif

   if (CLR)
      if (LD)
         if (pu.0&pd.0)
            q=q;
         else
            if (pu.0)
               if (q==9)
                  q=0;
               else
                  q=q+1;
               endif
            else
               if (pd.0)
                  if (q==0)
                     q=9;
                  else
                     q=q-1;
                  endif
               else
                  q=q;
               endif
            endif
         endif
      else
         q=D;
      endif
   else
      q=0;
   endif

   if (CLR)
      if (pu.0 & (q==0b1001))
         CR=0;
      else
         CR=1;
      endif

      if (pd.0 & (q==0b0000))
         BR=0;
      else
         BR=1;
      endif
   else
      CR=1; BR=1;
   endif

   Q=q;

   TP_pu=pu.0;
   TP_pd=pd.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output CPU,CPD;
output LD;
output D[4];
output Q[4];
output CR,BR;
output TP_pu,TP_pd;
bitr   tc[8];

   part TTL(CLR,CPU,CPD,LD,D,Q,CR,BR,TP_pu,TP_pd)

   tc=tc+1;

   if ((tc>78)&(tc<84)) D=5; endif
   if (tc==81) LD=0; else LD=1; endif

   if (tc<58)
      CPU=tc.1; CPD=1;
   else
      if (tc<89)
         CPD=tc.1; CPU=1;
      else
         CPD=0; CPU=0;
      endif
   endif

   if ((tc>5)&(tc<95)) CLR=1; else CLR=0; endif

ende

endlogic