{ ===================================================== }
{    74LP194                                            }
{ ===================================================== }
logicname 74LP194

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  CP;
input  S[2];
input  SL,SR;
input  D[4];
output Q[4];
output TP_p;
bitr   q[4];
bitr   p[2];

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (CLR)
      switch(S)
         case 0: q=q;
         case 1:
            q.0=SR;
            q.1:3=q.0:2;
         case 2:
            q.3=SL;
            q.0:2=q.1:3;
         case 3:
            q=D;
      endswitch
   else
      q=0;
   endif

   Q=q;

   TP_p=p.0;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output CP;
output S[2];
output SL,SR;
output D[4];
output Q[4];
output TP_p;
bitr   tc[8];

   part TTL(CLR,CP,S,SL,SR,D,Q,TP_p)

   tc=tc+1;

   if (tc<37) CP=tc.1; endif
   if (tc==19) SL=1; endif
   if (tc==7) SR=1; endif
   if ((tc>25)&(tc<29)) D=10; endif
   if (tc<15)
      S=1;
   else
      if (tc<27)
         S=2;
      else
         if (tc==27)
            S=3;
         else
            if (tc<31)
               S=2;
            else
               if (tc<33)
                  S=1;
               else
                  S=0;
               endif
            endif
         endif
      endif
   endif

   if ((tc>5)&(tc<41)) CLR=1; else CLR=0; endif

ende

endlogic