{ ===================================================== }
{    74LP195                                            }
{ ===================================================== }
logicname 74LP195

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  CP;
input  SEL;
input  J,K;
input  D[4];
output Q[4];
output NQ;
output TP_p;
bitr   q[4];
bitr   p[2];

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (CLR)
      if (p.0)
         if (SEL)
            switch(J,K)
               case 0,0: q.0=0;    q.1:3=q.0:2;
               case 0,1: q.0=q.0;  q.1:3=q.0:2;
               case 1,0: q.0=!q.0; q.1:3=q.0:2;
               case 1,1: q.0=1;    q.1:3=q.0:2;
            endswitch
         else
            q=D;
         endif
      else
         q=q;
      endif
   else
      q=0;
   endif

   Q=q;
   NQ=!q.3;

   TP_p=p.0;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output CP;
output SEL;
output J,K;
output D[4];
output Q[4];
output NQ;
output TP_p;
bitr   tc[8];

   part TTL(CLR,CP,SEL,J,K,D,Q,NQ,TP_p)

   tc=tc+1;

   if (tc<110) CP=tc.1; endif

   if ((tc>5)&(tc<115)) CLR=1; endif

   if ((tc>97)&(tc<101)) D=5; endif

   if (tc>6)
      if (tc==99)
         SEL=0;
      else
         SEL=1;
      endif
   endif

   if (tc==7)
      J=1; K=1;
   else
      if ((tc>25)&(tc<45))
         J=1; K=0;
      else
         if (tc==63)
            J=1; K=1;
         else
            if ((tc>63)&(tc<77))
               J=0; K=1;
            endif
         endif
      endif
   endif

ende

endlogic