{ ===================================================== }
{    74LP20                                             }
{ ===================================================== }
logicname 74LP20

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  A[4];
input  B[4];
output Y1,Y2;

   Y1 = !(A.0 & A.1 & A.2 & A.3);
   Y2 = !(B.0 & B.1 & B.2 & B.3);

ende

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{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output A[4];
output B[4];
output Y1,Y2;
bitr   tc[7];

   part TTL(A,B,Y1,Y2)

   tc=tc+1;

   switch(tc)
      case 3:  A=0;
      case 4:  A=1;
      case 5:  A=2;
      case 6:  A=3;
      case 7:  A=4;
      case 8:  A=5;
      case 9:  A=6;
      case 10: A=7;
      case 11: A=8;
      case 12: A=9;
      case 13: A=10;
      case 14: A=11;
      case 15: A=12;
      case 16: A=13;
      case 17: A=14;
      case 18: A=15;

      case 19: B=0;
      case 20: B=1;
      case 21: B=2;
      case 22: B=3;
      case 23: B=4;
      case 24: B=5;
      case 25: B=6;
      case 26: B=7;
      case 27: B=8;
      case 28: B=9;
      case 29: B=10;
      case 30: B=11;
      case 31: B=12;
      case 32: B=13;
      case 33: B=14;
      case 34: B=15;

   endswitch

ende

endlogic