{ ===================================================== }
{    74LP238                                            }
{ ===================================================== }
logicname 74LP238

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  G1,G2A,G2B;
input  D[3];
output Y[8];

   if(G1 & !G2A & !G2B)
      switch(D)
         case 0: Y=0b00000001;
         case 1: Y=0b00000010;
         case 2: Y=0b00000100;
         case 3: Y=0b00001000;
         case 4: Y=0b00010000;
         case 5: Y=0b00100000;
         case 6: Y=0b01000000;
         case 7: Y=0b10000000;
      endswitch
   else
      Y=0;
   endif

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output G1,G2A,G2B;
output D[3];
output Y[8];
bitr   tc[5];

   part TTL(G1,G2A,G2B,D,Y)

   tc=tc+1;

   switch(tc)
      case 5:  G1=1; G2A=0; G2B=0; D=0;
      case 6:  G1=1; G2A=0; G2B=0; D=1;
      case 7:  G1=1; G2A=0; G2B=0; D=2;
      case 8:  G1=1; G2A=0; G2B=0; D=3;
      case 9:  G1=1; G2A=0; G2B=0; D=4;
      case 10: G1=1; G2A=0; G2B=0; D=5;
      case 11: G1=1; G2A=0; G2B=0; D=6;
      case 12: G1=1; G2A=0; G2B=0; D=7;

      case 13: G1=0; G2A=0; G2B=0; D=7;
      case 14: G1=0; G2A=0; G2B=1; D=7;
      case 15: G1=0; G2A=1; G2B=0; D=7;
      case 16: G1=0; G2A=1; G2B=1; D=7;
      case 17: G1=1; G2A=0; G2B=1; D=7;
      case 18: G1=1; G2A=1; G2B=1; D=7;
   endswitch

ende

endlogic