{ ===================================================== }
{    74LP242                                            }
{ ===================================================== }
logicname 74LP242

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{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  GAB,GBA;
inout  A[4],B[4];
output TP_oa[4];
output TP_ob[4];
output TP_cnta;
output TP_cntb;
bitn   ia[4],ib[4];
bitn   oa[4],ob[4];
bitn   cnta,cntb;

   enable(A,ia,oa,cnta)
   enable(B,ib,ob,cntb)

   ob=!ia;
   oa=!ib;

   switch(GAB,GBA)
      case 1,1: cnta=1; cntb=0;
      case 0,0: cnta=0; cntb=1;
      case 1,0: cnta=0; cntb=0;
      case 0,1: cnta=0; cntb=0;
   endswitch

   TP_oa=oa;
   TP_ob=ob;
   TP_cnta=cnta;
   TP_cntb=cntb;

ende

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{    機能実行譜                                         }
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entity sim
output GAB,GBA;
output A[4],B[4];
output TP_oa[4];
output TP_ob[4];
output TP_cnta;
output TP_cntb;
bitr   tc[4];

   part TTL(GAB,GBA,A,B,TP_oa,TP_ob,TP_cnta,TP_cntb)

   tc=tc+1;

   switch(tc)
      case 3: GAB=0; GBA=0;
      case 4: GAB=0; GBA=1;
      case 5: GAB=1; GBA=0;
      case 6: GAB=1; GBA=1;
      case 7: GAB=1; GBA=0; A=5;
      case 8: GAB=1; GBA=0; B=10;
   endswitch

ende

endlogic