{ ===================================================== }
{    74LP251                                            }
{ ===================================================== }
logicname 74LP251

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{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  ST;
input  SEL[3];
input  D[8];
inout  Y,W;
output TP_oy;
output TP_ow;
output TP_cnty;
output TP_cntw;
bitn   y;
bitn   iy,iw;
bitn   ow,oy;
bitn   cnty,cntw;

   enable(Y,iy,oy,cnty)
   enable(W,iw,ow,cntw)

   switch(SEL)
      case 0: y=D.0;
      case 1: y=D.1;
      case 2: y=D.2;
      case 3: y=D.3;
      case 4: y=D.4;
      case 5: y=D.5;
      case 6: y=D.6;
      case 7: y=D.7;
   endswitch

   oy=y;
   ow=!y;

   cnty=!ST;
   cntw=!ST;

   TP_oy=oy;
   TP_ow=ow;
   TP_cnty=cnty;
   TP_cntw=cntw;
ende

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{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output ST;
output SEL[3];
output D[8];
output Y,W;
output TP_oy;
output TP_ow;
output TP_cnty;
output TP_cntw;
bitr   tc[4];

   part TTL(ST,SEL,D,Y,W,TP_oy,TP_ow,TP_cnty,TP_cntw)
   
   tc=tc+1;

   if ((tc>3)&(tc<14)) D=0x55; endif

   switch(tc)
      case 5:  SEL=0;
      case 6:  SEL=1;
      case 7:  SEL=2;
      case 8:  SEL=3;
      case 9:  SEL=4;
      case 10: SEL=5;
      case 11: SEL=6;
      case 12: SEL=7;
      case 14: ST=1;
   endswitch

ende

endlogic