{ ===================================================== }
{    74LP257                                            }
{ ===================================================== }
logicname 74LP257

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  G;
input  SEL;
input  A[4];
input  B[4];
inout  Y[4];
output TP_oy[4];
output TP_cnty;
bitn   iy[4];
bitn   oy[4];
bitn   cnty;

   enable(Y,iy,oy,cnty)
   
   if (SEL)
      oy=B;
   else
      oy=A;
   endif

   cnty=!G;

   TP_oy=oy;
   TP_cnty=cnty;
ende

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{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output G;
output SEL;
output A[4];
output B[4];
output Y[4];
output TP_oy[4];
output TP_cnty;
bitr   tc[5];

   part TTL(G,SEL,A,B,Y,TP_oy,TP_cnty)

   tc=tc+1;

   switch(tc)
      case 5:  G=1; SEL=0; A=0; B=0 ;
      case 6:  G=1; SEL=0; A=5; B=10;
      case 7:  G=0; SEL=0; A=5; B=10;
      case 8:  G=0; SEL=0; A=5; B=10;
      case 9:  G=0; SEL=0; A=5; B=10;
      case 10: G=0; SEL=1; A=5; B=10;
      case 11: G=0; SEL=1; A=5; B=10;
      case 12: G=0; SEL=1; A=5; B=10;
      case 13: G=1; SEL=0; A=5; B=10;
      case 14: G=1; SEL=0; A=0; B=0 ;
      case 15: G=1; SEL=0; A=0; B=0 ;
   endswitch

ende

endlogic