{ ===================================================== }
{    74LP259                                            }
{ ===================================================== }
logicname 74LP259

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  CP;
input  G;
input  D;
input  SEL[3];
output Q[8];
output TP_p;
bitr   q[8];
bitr   p[2];

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (CLR)
      if (p.0)
         if (G)
            q=q;
         else
            switch(SEL)
               case 0: q.0=D; q.1:7=q.1:7;
               case 1: q.1=D; q.2:7=q.2:7; q.0=q.0;
               case 2: q.2=D; q.3:7=q.3:7; q.0:1=q.0:1;
               case 3: q.3=D; q.4:7=q.4:7; q.0:2=q.0:2;
               case 4: q.4=D; q.5:7=q.5:7; q.0:3=q.0:3;
               case 5: q.5=D; q.6:7=q.6:7; q.0:4=q.0:4;
               case 6: q.6=D; q.7:7=q.7:7; q.0:5=q.0:5;
               case 7: q.7=D; q.0:6=q.0:6;
            endswitch
         endif
      else
         q=q;
      endif
   else
      q=0;
   endif

   Q=q;

   TP_p=p.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output CP;
output G;
output D;
output SEL[3];
output Q[8];
output TP_p;
bitr   tc[8];

   part TTL(CLR,CP,G,D,SEL,Q,TP_p)

   tc=tc+1;

   CP=tc.1;
   if ((tc>3)&(tc<70)) CLR=1; else CLR=0; endif

   switch(tc)
      case 5:  D=1; SEL=0; G=1;
      case 6:  D=1; SEL=0; G=0;
      case 7:  D=1; SEL=0; G=0;
      case 8:  D=1; SEL=0; G=0;
      case 9:  D=1; SEL=0; G=1;

      case 12: D=0; SEL=1; G=1;
      case 13: D=0; SEL=1; G=0;
      case 14: D=0; SEL=1; G=0;
      case 15: D=0; SEL=1; G=0;
      case 16: D=0; SEL=1; G=1;

      case 21: D=1; SEL=2; G=1;
      case 22: D=1; SEL=2; G=0;
      case 23: D=1; SEL=2; G=0;
      case 24: D=1; SEL=2; G=0;
      case 25: D=1; SEL=2; G=1;

      case 29: D=0; SEL=3; G=1;
      case 30: D=0; SEL=3; G=0;
      case 31: D=0; SEL=3; G=0;
      case 32: D=0; SEL=3; G=0;
      case 33: D=0; SEL=3; G=1;

      case 37: D=1; SEL=4; G=1;
      case 38: D=1; SEL=4; G=0;
      case 39: D=1; SEL=4; G=0;
      case 40: D=1; SEL=4; G=0;
      case 41: D=1; SEL=4; G=1;

      case 45: D=0; SEL=5; G=1;
      case 46: D=0; SEL=5; G=0;
      case 47: D=0; SEL=5; G=0;
      case 48: D=0; SEL=5; G=0;
      case 49: D=0; SEL=5; G=1;

      case 53: D=1; SEL=6; G=1;
      case 54: D=1; SEL=6; G=0;
      case 55: D=1; SEL=6; G=0;
      case 56: D=1; SEL=6; G=0;
      case 57: D=1; SEL=6; G=1;

      case 61: D=0; SEL=7; G=1;
      case 62: D=0; SEL=7; G=0;
      case 63: D=0; SEL=7; G=0;
      case 64: D=0; SEL=7; G=0;
      case 65: D=0; SEL=7; G=1;

      default: G=1;
   endswitch

ende

endlogic