{ ===================================================== }
{    74LP273                                            }
{ ===================================================== }
logicname 74LP273

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  CP;
input  D[8];
output Q[8];
output TP_p;
bitr   q[8];
bitr   p[2];

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (CLR)
      if (p.0)
         q=D;
      else
         q=q;
      endif
   else
      q=0;
   endif

   Q=q;

   TP_p=p.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output CP;
output D[8];
output Q[8];
output TP_p;
bitr   tc[5];

   part TTL(CLR,CP,D,Q,TP_p)

   tc=tc+1;

   if (tc<13) CP=tc.1; endif

   if ((tc>3)&(tc<15)) CLR=1; else CLR=0; endif

   switch(tc)
      case 6:  D=0x55;
      case 7:  D=0x55;
      case 8:  D=0x55;

      case 10: D=0xAA;
      case 11: D=0xAA;
      case 12: D=0xAA;
   endswitch

ende

endlogic