{ ===================================================== }
{    74LP280                                            }
{ ===================================================== }
logicname 74LP280

{ ----------------------------------------------------- }
{    手続き譜                                           }
{ ----------------------------------------------------- }
procedure hc
input  D[4];
output Q[3];

   switch(D)
      case 0b0000: Q=0;
      case 0b0001: Q=1;
      case 0b0010: Q=1;
      case 0b0011: Q=2;
      case 0b0100: Q=1;
      case 0b0101: Q=2;
      case 0b0110: Q=2;
      case 0b0111: Q=3;
      case 0b1000: Q=1;
      case 0b1001: Q=2;
      case 0b1010: Q=2;
      case 0b1011: Q=3;
      case 0b1100: Q=2;
      case 0b1101: Q=3;
      case 0b1110: Q=3;
      case 0b1111: Q=4;
   endswitch
endp

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  D[9];
output EV,OD;
output TP_no[4];
bitn   ctl[3],cth[3];
bitn   no[4];

   ctl=hc(D.0:3);
   cth=hc(D.4:7);

   if (D.8)
      switch(ctl)
         case 0:
            switch(cth)
               case 0: no=1;
               case 1: no=2;
               case 2: no=3;
               case 3: no=4;
               case 4: no=5;
            endswitch
         case 1:
            switch(cth)
               case 0: no=2;
               case 1: no=3;
               case 2: no=4;
               case 3: no=5;
               case 4: no=6;
            endswitch
         case 2:
            switch(cth)
               case 0: no=3;
               case 1: no=4;
               case 2: no=5;
               case 3: no=6;
               case 4: no=7;
            endswitch
         case 3:
            switch(cth)
               case 0: no=4;
               case 1: no=5;
               case 2: no=6;
               case 3: no=7;
               case 4: no=8;
            endswitch
         case 4:
            switch(cth)
               case 0: no=5;
               case 1: no=6;
               case 2: no=7;
               case 3: no=8;
               case 4: no=9;
            endswitch
      endswitch
   else
      switch(ctl)
         case 0:
            switch(cth)
               case 0: no=0;
               case 1: no=1;
               case 2: no=2;
               case 3: no=3;
               case 4: no=4;
            endswitch
         case 1:
            switch(cth)
               case 0: no=1;
               case 1: no=2;
               case 2: no=3;
               case 3: no=4;
               case 4: no=5;
            endswitch
         case 2:
            switch(cth)
               case 0: no=2;
               case 1: no=3;
               case 2: no=4;
               case 3: no=5;
               case 4: no=6;
            endswitch
         case 3:
            switch(cth)
               case 0: no=3;
               case 1: no=4;
               case 2: no=5;
               case 3: no=6;
               case 4: no=7;
            endswitch
         case 4:
            switch(cth)
               case 0: no=4;
               case 1: no=5;
               case 2: no=6;
               case 3: no=7;
               case 4: no=8;
            endswitch
      endswitch
   endif

   switch(no)
      case 0: EV=1; OD=0;
      case 1: EV=0; OD=1;
      case 2: EV=1; OD=0;
      case 3: EV=0; OD=1;
      case 4: EV=1; OD=0;
      case 5: EV=0; OD=1;
      case 6: EV=1; OD=0;
      case 7: EV=0; OD=1;
      case 8: EV=1; OD=0;
      case 9: EV=0; OD=1;
   endswitch

   TP_no=no;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output D[9];
output EV,OD;
output TP_no[4];
bitr   tc[10];

   part TTL(D,EV,OD,TP_no)
   
   tc=tc+1;

   D=tc.0:8;

ende

endlogic