{ ===================================================== }
{    74LP283                                            }
{ ===================================================== }
logicname 74LP283

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  A[4],B[4];
input  CI;
output Q[4];
output CO;
bitn   a[5];
bitn   b[5];
bitn   c[5];
bitn   q[5];

   c.0=CI;
   a.0:3=A;
   b.0:3=B;

   q=a+b+c;

   Q.0:3=q.0:3;
   CO=q.4;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output A[4],B[4];
output CI;
output Q[4];
output CO;
bitr   tc[9];

   part TTL(A,B,CI,Q,CO)

   tc=tc+1;

   A=tc.0:3;
   B=tc.4:7;
   CI=tc.8;
ende

endlogic