{ ===================================================== }
{    74LP354                                            }
{ ===================================================== }
logicname 74LP354

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  DC;
input  SC;
input  G1,G2,G3;
input  SEL[3];
input  D[8];
inout  Y,W;
output TP_y;
output TP_cnty;
output TP_d[8];
output TP_sel[3];
output TP_oy;
output TP_ow;
bitr   sel[3];
bitr   d[8];
bitn   y;
bitn   iy,oy,cnty;
bitn   iw,ow,cntw;

   enable(Y,iy,oy,cnty)
   enable(W,iw,ow,cntw)

   if (SC)
      sel=SEL;
   else
      sel=sel;
   endif

   if (DC)
      d=D;
   else
      d=d;
   endif

   switch(sel)
      case 0: y=d.0;
      case 1: y=d.1;
      case 2: y=d.2;
      case 3: y=d.3;
      case 4: y=d.4;
      case 5: y=d.5;
      case 6: y=d.6;
      case 7: y=d.7;
   endswitch

   if (!G1 & !G2 & G3) cnty=1; cntw=1; endif

   oy=y;
   ow=!y;

   TP_y=y;
   TP_cnty=cnty;
   TP_d=d;
   TP_sel=sel;
   TP_oy=oy;
   TP_ow=ow;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output DC;
output SC;
output G1,G2,G3;
output SEL[3];
output D[8];
output Y,W;
output TP_y;
output TP_cnty;
output TP_d[8];
output TP_sel[3];
output TP_oy;
output TP_ow;
bitr   tc[6];

   part TTL(DC,SC,G1,G2,G3,SEL,D,Y,W,TP_y,TP_cnty,TP_d,TP_sel,TP_oy,TP_ow)

   tc=tc+1;

   switch(tc)
      case 5: D.0=1;
      case 6: D.0=1; DC=1;
      case 7: D.0=1;

      case 7: SEL=1;
      case 8: SEL=1; SC=1;
      case 9: SEL=1;

      case 10: D.1=1;
      case 11: D.1=1; DC=1;
      case 12: D.1=1;

      case 13: SEL=2;
      case 14: SEL=2; SC=1;
      case 15: SEL=2;

      case 16: D.2=1;
      case 17: D.2=1; DC=1;
      case 18: D.2=1;

      case 19: SEL=3;
      case 20: SEL=3; SC=1;
      case 21: SEL=3;

      case 22: D.3=1;
      case 23: D.3=1; DC=1;
      case 24: D.3=1;

      case 25: SEL=4;
      case 26: SEL=4; SC=1;
      case 27: SEL=4;

      case 28: D.4=1;
      case 29: D.4=1; DC=1;
      case 30: D.4=1;

      case 31: SEL=5;
      case 32: SEL=5; SC=1;
      case 33: SEL=5;

      case 34: D.5=1;
      case 35: D.5=1; DC=1;
      case 36: D.5=1;

      case 37: SEL=6;
      case 38: SEL=6; SC=1;
      case 39: SEL=6;

      case 40: D.6=1;
      case 41: D.6=1; DC=1;
      case 42: D.6=1;

      case 43: SEL=7;
      case 44: SEL=7; SC=1;
      case 45: SEL=7;

      case 46: D.7=1;
      case 47: D.7=1; DC=1;
      case 48: D.7=1;

      case 50: G1=0; G2=0; G3=1;
      case 51: G1=0; G2=1; G3=0;
      case 52: G1=0; G2=1; G3=1;
      case 53: G1=1; G2=0; G3=0;
      case 54: G1=1; G2=0; G3=1;
      case 55: G1=1; G2=1; G3=0;
      case 56: G1=1; G2=1; G3=1;
   endswitch

ende

endlogic