{ ===================================================== }
{    74LP373                                            }
{ ===================================================== }
logicname 74LP373

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  LE,OE;
input  D[8];
inout  Q[8];
output TP_q[8];
bitr   q[8];
bitn   iq[8],oq[8],cq;

   enable(Q,iq,oq,cq)

   if (LE)
      q=D;
   else
      q=q;
   endif

   cq=!OE;

   oq=q;

   TP_q=q;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output LE,OE;
output D[8];
output Q[8];
output TP_q[8];
bitr   tc[5];

   part TTL(LE,OE,D,Q,TP_q)

   tc=tc+1;

   switch(tc)
      case 5:  LE=1; D=0x55;
      case 6:  LE=1; D=0xaa;
      case 7:  LE=1; D=0x55;
      case 8:  LE=0; D=0x55;
      case 9:  LE=0; D=0xaa;
      case 10: LE=0; D=0x55;
      case 11: LE=1; D=0x55;
      case 12: LE=1; D=0xaa;
      case 13: LE=0; D=0x55;
      case 14: LE=0; D=0x55;
      case 15: LE=1; D=0x55;
      default: LE=1; D=0x55;
   endswitch

ende

endlogic