{ ===================================================== }
{    74LP374                                            }
{ ===================================================== }
logicname 74LP374

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CP,OE;
input  D[8];
inout  Q[8];
output TP_q[8];
output TP_p;
bitr   q[8];
bitr   p[2];
bitn   iq[8],oq[8],cq;

   enable(Q,iq,oq,cq)

   if (CP)
      if (p==0)
         p=1;
      else
         if (p==1)
            p=2;
         else
            p=p;
         endif
      endif
   else
      p=0;
   endif

   if (p.0)
      q=D;
   else
      q=q;
   endif

   cq=!OE;

   oq=q;

   TP_q=q;
   TP_p=p.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CP,OE;
output D[8];
output Q[8];
output TP_q[8];
output TP_p;
bitr   tc[5];

   part TTL(CP,OE,D,Q,TP_q,TP_p)

   tc=tc+1;

   CP=tc.1;

   switch(tc)
      case 1: D=0x55;
      case 2: D=0x55;
      case 3: D=0x55;
      case 4: D=0x55;
      case 5: D=0xaa;
      case 6: D=0xaa;
      case 7: D=0xaa;
      case 8: D=0xaa;
   endswitch

ende

endlogic