{ ===================================================== }
{    74LP375                                            }
{ ===================================================== }
logicname 74LP375

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  G1,G2;
input  D[4];
output PQ[4],NQ[4];
bitr   q[4];

   if (G1)
      q.0:1=D.0:1;
   else
      q.0:1=q.0:1;
   endif

   if (G2)
      q.2:3=D.2:3;
   else
      q.2:3=q.2:3;
   endif

   PQ=q;
   NQ=!q;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output G1,G2;
output D[4];
output PQ[4],NQ[4];
bitr   tc[5];

   part TTL(G1,G2,D,PQ,NQ)

   tc=tc+1;

   switch(tc)
      case 3:  D=5; G1=1; G2=1;
      case 4:  D=5; G1=1; G2=1;
      case 5:  D=5; G1=0; G2=1;
      case 6:  D=5; G1=0; G2=1;
      case 7:  D=0; G1=0; G2=0;
      case 8:  D=0; G1=0; G2=0;
      case 9:  D=0; G1=0; G2=0;
      case 10: D=0; G1=1; G2=0;
      case 11: D=0; G1=1; G2=0;
      case 12: D=0; G1=1; G2=1;
      case 13: D=0; G1=1; G2=1;
      case 14: D=0; G1=1; G2=1;
      case 15: D=0; G1=1; G2=1;
      default: G1=1; G2=1;
   endswitch

ende

endlogic