{ ===================================================== }
{    74LP42                                             }
{ ===================================================== }
logicname 74LP42

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  A[4];
output Y[10];
bitn   y[10];

   switch(A)
      case 0: y=0b0000000001;
      case 1: y=0b0000000010;
      case 2: y=0b0000000100;
      case 3: y=0b0000001000;
      case 4: y=0b0000010000;
      case 5: y=0b0000100000;
      case 6: y=0b0001000000;
      case 7: y=0b0010000000;
      case 8: y=0b0100000000;
      case 9: y=0b1000000000;
   endswitch

   Y=!y;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output A[4];
output Y[10];
bitr   tc[4];

   part TTL(A,Y)

   tc=tc+1;

   A=tc;

ende

endlogic