{ ===================================================== }
{    74LP51                                             }
{ ===================================================== }
logicname 74LP51

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  A[4];
input  B[6];
output Y1,Y2;

   Y1 = !((A.0 & A.1) | (A.2 & A.3));

   Y2 = !((B.0 & B.1 & B.2)
      |   (B.3 & B.4 & B.5));

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output A[4];
output B[6];
output Y1,Y2;
bitr   tc[7];

   part TTL(A,B,Y1.Y2)

   tc=tc+1;

   A=tc.0:3;
   B=tc.0:5;

ende

endlogic