{ ===================================================== }
{    74LP597                                            }
{ ===================================================== }
logicname 74LP597

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  CLR;
input  G;
input  SCK,RCK;
input  SI;
input  SL;
input  D[8];
output QH;
output TP_q[8];
output TP_d[8];
output TP_pa;
output TP_pb;
bitr   q[8];
bitr   d[8];
bitr   pa[2],pb[2];

   if (SCK)
      if (pa==0)
         pa=1;
      else
         if (pa==1)
            pa=2;
         else
            pa=pa;
         endif
      endif
   else
      pa=0;
   endif

   if (RCK)
      if (pb==0)
         pb=1;
      else
         if (pb==1)
            pb=2;
         else
            pb=pb;
         endif
      endif
   else
      pb=0;
   endif
   
   if (CLR)
      if (SL)
         if (pa.0)
            q.0=SI;
            q.1:7=q.0:6;
         else
            q=q;
         endif
      else
         q=d;
      endif
   else
      q=0;
   endif

   if (pb.0)
      d=D;
   else
      d=d;
   endif

   QH=q.7;

   TP_q=q;
   TP_d=d;
   TP_pa=pa.0;
   TP_pb=pb.0;
ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output CLR;
output G;
output SCK,RCK;
output SI;
output SL;
output D[8];
output QH;
output TP_q[8];
output TP_d[8];
output TP_pa;
output TP_pb;
bitr   tc[8];

   part TTL(CLR,G,SCK,RCK,SI,SL,D,QH,TP_q,TP_d,TP_pa,TP_pb)

   tc=tc+1;
   
   if (tc<41) SCK=tc.1; endif
   if ((tc>3)&(tc<55)) CLR=1; else CLR=0; endif
   if (tc==45) RCK=1; endif
   if (tc==50) SL=0; else SL=1; endif
   if ((tc>42)&(tc<48)) D=0x55; endif
   if ((tc>5)&(tc<9)) SI=1; endif
   if ((tc>37)&(tc<41)) SI=1; endif
   if ((tc>20)&(tc<24)) RCK=1; endif

ende

endlogic